1. Field of the Invention
The present invention relates in general to the field of information processing, and more specifically to a system and method for efficiently transferring data using latches in a datapath.
2. Description of the Related Art
Latches are one of the most common digital circuits used in modern data processing devices. In multi-gigahertz processor designs, the setup and launch delay through latches have become a significant portion of the cycle time. The sum of the setup time and launch delay of the latch, if large, exacerbates the delay in the critical timing paths. An optimal latch design would have a minimum combined sum of setup time (din to clock) and launch (clock to dout).
Master-slave latches are commonly used to propagate data through various datapaths within a data processing system. Such latches typically use multiple clocks to enable the master and the slave portions of the latch to receive data inputs and to propagate the data within the data processing system. While the setup and hold time for master-slave latches has been acceptable in many prior art processors, they present design problems in processors with multi-gigahertz speeds.
An alternative to a master-slave latch is the pulse latch, which has a minimal setup and launch delay time and, therefore, is ideal for optimizing critical speed paths. The pulse latch, however, requires a controlled pulse clock and the pulse generation circuit is very sensitive to process variation, which can affect the robustness of the pulse latch.
Another problem with prior art pulse generation circuitry is that a single pulse generator is generally used to generate pulses for an entire datapath. A properly shaped pulse is produced initially. However, the RC network of the metal wire used to transmit the pulse acts as a low-pass filter that attenuates the pulse. As the pulse propagates across the latches in the datapath, the pulse degrades and, therefore, successive cells in the datapath receive a degraded pulse signal. By the time the pulse reaches the last data cell in the datapath, the signal may have degraded significantly.
It is possible to implement signal shaping solutions to solve the problem of pulse signal variability for a particular process. Therefore, the pulse degradation problem can be solved by remedial measures for a particular feature size of a specific process. The solution for one process and feature size, however, does not readily translate to other feature sizes.
In view of the foregoing, it is apparent that there is a need for an improved latch triggering circuit that provides reduced circuit complexity. Furthermore, there is a need for a system and method for providing accurate pulse shaping that can be scaled across various processes. More specifically, there is a need for a pulse latch topology that can be used in a path where minimal setup and launch delay is required. In addition, the conventional master-slave latch topology must be implemented in a path where data setup is significantly ahead of the clock and the hold time is critical.
Accordingly, a need exists for logic circuitry that minimizes the propagation time for data transferred by latches in a datapath. More particularly, there is a need for improved logic to minimize the setup time and launch delay through the latches that are becoming a significant portion of the cycle time in modern processors. There is also a need for an improved apparatus and method to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
Where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.